The performance, density, and cost of integrated circuit (IC) chips have been improving at a dramatic rate. Much of the improvement has been due to the ability to scale MOSFETs to increasingly smaller dimensions, resulting in higher speed and higher functional density. The increase in both clock frequency and transistor counts per chip also results in the increase in power dissipation per chip. Innovative solutions are needed to improve the performance of the MOSFETs in order to meet the requirements of overall circuit and device performance of the IC chip.
FIG. 1A illustrates a top-down view of a conventional MOSFET device 100 having a gate 110, a source 132 and a drain 135 in an active region 130 in a semiconductor substrate. Active region 130 may be bordered on some or all sides by isolation (or field) regions 160, which separate MOSFET 100 from other devices in an IC. The extent of gate 110 along the “y” direction shown in FIG. 1 is called the length L of the gate, while the extent of source 132, drain 135, or active region along the z direction is called the width W of the source, drain, or active region, respectively. Width W is also referred to as the width of MOSFET 100 and the width of gate 110.
FIG. 1B illustrates a cross-sectional view of MOSFET 100 along line B-B′ in FIG. 1. As shown in FIG. 1B, gate 110 is separated from substrate 180 by a gate oxide layer 120. Source 132 and drain 135 are diffusion regions on two opposite sides of gate 110 and are formed in a well region 170 in substrate 180. Source 132, drain 135, and well 170 are typically formed by introducing dopants in corresponding regions in substrate 180 using a doping process. A typical doping process includes one or more ion implantation steps, in which dopant ions are implanted into selected areas of substrate 180, and a subsequent diffusion step, in which the substrate is subjected to thermal treatment, allowing the implanted dopants to diffuse and settle into corresponding regions of the substrate. Source 132 and drain 135 are typically doped with dopants having a conductivity type that is the opposite of that of the dopants in well 170. For example, if well 170 is doped with p-type dopants, the source and drain are formed with n-type dopants, or vice versa. Also, dopant concentrations in source and drain regions 132 and 135 are typically much heavier than that in well 170. MOSFETs having n-type source and drain are known as NMOSFETs and MOSFETs having p-type source and drain are known as PMOSFETs.
As shown in FIG. 1B, MOSFET 100 further includes source/drain extensions 142 and 145, which are diffusion regions also formed in well region 170 and which are shallower than source and drain regions 132 and 135. Souce/drain extensions 142 and 145 are typically formed by doping the corresponding regions of substrate 180 with dopants having the same conductivity type as the dopants in the source and drain regions 132 and 135. Dopant concentrations in source/drain extensions 142 and 145 are typically lighter than those in source and drain regions 132 and 135 but heavier than those in well 170. MOSFET 100 further comprises spacers 152 and 155 located on the sidewalls of gate 110. Spacers 152 and 155 are typically made of dielectric materials which further isolate the gate from the source and drain to prevent the build-up of device capacitance.
Isolation regions 160 may be formed using conventional shallow trench isolation (STI) techniques. The STI regions 160 are usually formed early in a process for fabricating MOSFET 100 by etching shallow trenches (typically less than 0.5 μm deep) into substrate 180, filling the trenches with a dielectric material, such as silicon dioxide (oxide), and then planarizing the deposited oxide with chemical mechanical polishing.
MOSFET 100 behaves like a switch. When a sufficient threshold voltage, Vt, is applied to the gate, a conductive channel 118 is formed in the part of the substrate immediately under gate oxide 120 and between the two source/drain extensions 142 and 145. The device is then turned “on” and relatively large currents can flow between the source and drain through channel 118. The distance that charge carriers travel between the source/drain extensions 142 and 145 is referred to as the effective length, Leff, of the MOSFET.
Ideally, when MOSFET 100 is “off”, i.e., when the voltage applied to the gate is lower than Vt, there is no current flow. In practice, however, the device is usually characterized by a small amount of unwanted leakage current Ioff, which flows or “leaks” between any pair of source, drain and gate in an off-state of the device. The on/off ratios (Ion/Ioff) of MOSFET 100 are common figures of merit and benchmark for transistor performance comparisons, where Ion is the current that flows between the source and drain when a maximum logic voltage, typically called VDD or VCC, is applied to both the gate and the drain while the source is grounded. Since leakage currents cause unnecessary heat generation and can cause problems related to the dissipation of excess heat, higher Ioff values or lower on/off ratios indicate degraded transistor performance.
As MOSFET devices become smaller, problems due to off-state leakage currents become more serious. There are several causes of off-state leakage currents, some of which are particularly related to device scaling, such as the so-called edge (or corner) leakage associated with the STI technology for forming isolation regions 160. STI is the technology of choice for complimentary metal-oxide-silicon (CMOS) ultra large scale integrated circuits (ULSI) when the gate length of MOSFETs shrink below the quarter micron regime. It is replacing the older isolation technologies, such as local oxidation of silicon (LOCOS), because it provides planarized active and field regions and it avoids the “bird's beak” associated with LOCOS, which extends beyond the mask-defined limit of the isolation regions and encroaches into the active region of a MOSFET. The planarized surfaces of STI are critical to meet the tighter lithography requirements associated with the fabrication of smaller devices, and the absence of the bird's beak improves the packing density and is helpful in scaling to smaller design rules.
The STI technology, however, also introduces new problems with leakage currents. A common STI leakage problem is called edge (or corner leakage), which occurs if the STI trench sidewall edges (or STI corners) 165 are too sharp. FIG. 1C is a cross-sectional view of MOSFET 100 along line C-C′ in FIG. 1. The STI corners 165 can lead to a high fringing electric field, which may create inversion in the part of substrate 180 near STI corners 165 and thus parasitic transistors with a lower threshold voltage in the edge parts 102 and 103 of the MOSFET in parallel to the normal transistor in the middle part 101 of the MOSFET. This is especially a problem in circuits which operate with dual voltages and in embedded flash processes, since transistors there can have different thicknesses of gate oxides. While further rounding of the STI corners 165 may help alleviate the problem, reducing STI corner sharpness often requires substantial process modifications and additional process steps, resulting in increased manufacturing cost and lower manufacturing efficiency.
The edge (or corner) leakage may also occur when electrons or negatively charged ions get trapped along STI trench sidewalls 162 during the process for forming the STI 160. If the MOSFET 100 is a NMOSFET, in which the region under gate 110 is doped with p-type dopants, the trapped electrons or negatively charged ions at the trench sidewall 162 may diffuse into the surrounding regions, causing the part of well 170 near the trench sidewall 162 to have a lower dopant concentration. The lower dopant concentration between the source and drain regions means a lower threshold voltage so that the corresponding part of the NMOSFET can turn on when the voltage applied to gate 110 is lower than Vt, resulting in the so-called side-wall leakage current flowing between the source and drain. While field implants may be used in the device to reduce the sidewall leakage, a higher field implant dose results in larger capacitance and degraded device performance.
Still another problem associated with STI is the so-called inverse narrow width effect (INWE). As shown in FIG. 1C, the STI profile includes divots 167 that occur during the process for forming the STI as part of the effort to round the STI corners 165. The divots are a primary cause of the INWE, which is a parasitic phenomenon of lower effective threshold voltage as the width W of the MOSFET 100 becomes smaller. The effect of INWE can be seen from the plots of FIGS. 2A-2D. FIG. 2A plots the relationship between device width and the device threshold voltage, Vth. For device widths, W, well above 1 μm, segment 60 indicates that the threshold voltage remains relatively steady with changes in device width. However, when device width drops below about 1 μm, as depicted by segment 50, the threshold voltage of the device decreases at a much greater rate as the device width decreases. Representative values for the graph of FIG. 2A are provided in FIG. 2B.
Leakage currents can also occur due to the INWE because the presence of a lower threshold voltage, Vt, produces higher off-state leakage currents. FIG. 2C plots the relationship between device width and the device off-state current, Ioff. As depicted in FIG. 2C, For widths well above 1 μm, Ioff remains relatively steady with changes in the device width as indicated by segment 80. However, as device width drops below about 1 μm as indicated by segment 70, Ioff increases with reduced device width at a much greater rate. Representative values for the graph of FIG. 2C are provided in FIG. 2D.
Another cause for off-state leakage currents is related to effective gate oxide thinning, which occurs over a device lifetime due to imperfections in the gate oxide layer 120 and stresses on the device such as high applied voltage levels. The effective thinning of the gate oxide film 120 increases the likelihood of oxide breakdown caused by the well-known “hot-carrier effect” which is more prominent at the drain side of edges 102 and 103 of MOSFET 100 near gate 110 (FIG. 1C).
In short, leakage currents can come from many different sources, and Ioff test failures represent a major source of device failures and considerable economic waste. Therefore there is a need for an improved MOSFET design and fabrication approach that can alleviate the problems of leakage currents associated with manufacturing defects and device degradation without adversely affecting the electrical output characteristics of the device.